Three things decide how a board gets panelized: the outline, the thickness, and what sits next to the separation line. Settle those and most of the remaining parameters follow from the line the boards will run on.
Getting them wrong is expensive because the cost lands on the last operation. By the time a panel reaches depaneling, the boards have been printed, placed, reflowed and inspected, and every component on them is already paid for.
A board that cracks along a V-score costs you a finished assembly, not a piece of bare laminate.
When Does a Board Need to Be Panelized?
The threshold is a line limit, not a design preference. OnVenture Electronics' SMT lines, any board smaller than 50mm × 50mm must be panelized before it can run.
The upper limit for an assembled board is 774mm × 710mm. Below the lower limit the board cannot be gripped and transported reliably, and small boards waste line cadence if they run one at a time.
Two other cases force panelization regardless of size:
- Non-rectangular outlines. Circular, rounded and odd-shaped boards have no straight edge for the conveyor rails to hold. They run in an array with break-away fields added.
- Components at or over the board edge. Connectors that overhang the outline need a rail to protect them through transport and reflow.
Panel size at the upper end is limited by three things at once: the rail adjustment range, the printer table, and the usable width of the reflow oven. The smallest of the three sets the ceiling.
Which PCB Panelization Method: V-Score or Tab Routing?
Work the three variables in order. Most boards resolve at step two.
Step one, the outline. A rectangular board with straight separation paths can use V-score. Curved edges, notches and irregular outlines go to tab routing.
Step two, the thickness. V-score cuts a groove from both faces with a 30° or 45° blade and leaves a remaining web of roughly one third of the board thickness.
Below about 1.0mm that web is too thin to carry the panel's own weight through transport and reflow, and boards start separating before they reach depaneling. Thin boards go to tab routing.
Step three, what sits beside the separation line. If a large ceramic capacitor or a BGA sits next to the score, step back to tab routing or rearrange the array so the score line moves away.
Mixing both methods on one panel is normal practice. Straight sides run V-score, curved or component-dense sides run tab routing. Each separation line gets judged on its own conditions.
On tab routing, the connecting bridge carries a row of mouse bites, commonly three or five holes at around 0.5mm diameter. Three-hole tabs suit smaller panels.
The broken tab leaves a scalloped burr on the board edge. Boards that seat against an enclosure or slide into a rail need a drawing note specifying whether that edge is milled flat.
Keep traces off the bridge, and keep components clear of both ends of it.
Where Do Rails and Fiducials Go on a PCB Panel?
Rails give the conveyor and the clamping mechanism something to hold, and they keep edge components off the rails.
They belong on the two longer parallel edges of the panel, and the transport direction needs to be marked on the file. Without that marking, rails can end up on the wrong pair of edges. Common rail width runs 5mm to 10mm.
Fiducials are what the placement machine uses to locate the board optically. They work in three layers:
- Panel level: at least three, in an asymmetric pattern. The asymmetry is what stops a panel from being loaded 180° out.
- Board level: two or three per individual board, on opposite corners.
- Local: added next to fine-pitch BGA and QFN packages for local coordinate correction.
A common specification is 1.0mm of exposed copper with 2mm or more of clearance from soldermask and silkscreen.
That clearance matters more than it looks. Placement on Venture Electronics' lines holds ±22µm at 3σ and printing holds ±25µm at 6σ. A fiducial the camera reads poorly gives that accuracy away before the first component lands.
Fiducials cannot sit under components, and they cannot sit in an area that depaneling will cut off.
Tooling holes position the panel mechanically during printing, placement and depaneling. They are typically 3.0mm to 4.0mm, non-plated, placed diagonally on the rails.
How Much Edge Clearance Do Panelized Boards Need?
This is the most under-specified item on a panel drawing and the one that produces the most scrap.
Against a V-score line, keep component bodies 3mm or more from the groove. For stress-sensitive parts, open that to 5mm or more:
- Large ceramic capacitors, 1206 and above. Bending stress cracks the ceramic body internally.
- BGA and other large-footprint packages, where stress travels through the solder balls.
- Crystals and ceramic resonators, which have mechanically fragile internal structures.
- Connectors, stiff enough to concentrate stress into their own pads.
Against tab routing, apply the same thinking to the distance from the bridge. Breaking a bridge applies a moment across the board face, and whatever sits nearest takes most of it.
Nothing catches these cracks at the time they happen. Optical inspection does not see inside a ceramic body, and a functional test often passes. The board ships well and fails weeks later in the field.
Confirming that a field failure came from depaneling means going to dye and pry or cross-sectioning after the fact. Edge clearance has to be right in the layout rather than screened at final inspection.
Two more items belong in the same check:
- Component height is not capped by a fixed line limit — boards with components taller than 25mm can still be built. What has to be checked is clearance: the component against the transport rails, and against whatever carrier or fixture the panel runs in. Anything that can be knocked during transport or stacking should be flagged at DFM review.
- Components overhanging the outline need clearance designed into the array.
Tall components and carrier design are the same conversation, which is where the panel support scheme comes in.
How Do You Support Thin, Flex, and Odd-Shaped Panels?
Correct panel parameters still leave one failure mode open: the panel sags or flexes during the process.
Rigid boards run down to 0.15mm and flex down to 0.05mm. At those thicknesses the panel has almost no stiffness of its own. Bare-board flatness is held to the IPC-6012 limit of 0.75% warp and twist for boards carrying surface-mount components, but a panel loaded with paste and parts behaves differently from a bare one.
Four cases call for a carrier:
- Boards under about 0.8mm, which dip under squeegee pressure during printing and sag in the oven.
- Flex and rigid-flex, which have no self-supporting structure at all.
- Odd-shaped arrays with large cutouts, where the removed material takes the stiffness with it.
- Long panels, where sag grows with the unsupported span.
Venture Electronics' fixture and carrier tooling is designed and built in house, machined from composite stone and ESD-safe polymers.
SMT reflow carriers hold the panel flat and shield bottom-side components through the oven. Wave solder pallets mask the surface-mount side and expose only the through-hole leads.
Design the carrier alongside the panel, not after it. Locating pins on the carrier follow the tooling holes in the array, so a panel finalized without the carrier in mind usually means the tooling gets cut twice.
When Should a PCB Panel Layout Be Reviewed?
Before Gerber release. The panel constrains both bare-board fabrication and assembly, so changing it after the boards are cut means cutting them again.
Panelization can come from the design side or from the manufacturing side. When the factory proposes it, the array can be set directly against the rail range, the router bit diameter and the depaneling equipment, which removes a round trip.
Venture Electronics' engineering team reviews panelization as part of itsDFM and DFA analysis, alongside stack-up, footprints and test point access, with feedback returned against specific coordinates.
Revisit the array when the volume stage changes. Prototype and small-batch builds favour flexibility: fewer boards per panel, simple separation, easy single-board rework.
Production favours material yield and line cadence, and more boards per panel spreads changeover and printing time across more units. A larger panel also sags more, so the support scheme has to be re-checked rather than carried over.
With six SMT lines covering single prototypes through low-volume production, that re-evaluation happens inside one facility rather than as part of a supplier change.
Values above that are not attributed to Venture Electronics' lines are common industry practice, and working numbers should be set against the line that will actually build the boards.
Confirm Your PCB Panel Layout Before File Release
Board size, outline, thickness and edge clearance are the four items that decide whether a panel survives depaneling, and all four have to be settled before files are released.
Send the current array with your Gerber files for a manufacturing-side review, and check it againstVenture Electronics' PCB assembly capabilities to confirm the array fits the line that will build it.
FAQ about PCB Panelization for SMT Assembly
Q1: What is the smallest board that can run without panelization?
On Venture Electronics'SMT assembly lines, boards under 50mm × 50mm have to be panelized before they can run. Below that size the board cannot be held and transported reliably through printing, placement and reflow.
Q2: What is the minimum board thickness for V-score?
Around 1.0mm is the common working limit, with some lines setting it at 1.2mm. Below that the remaining web left by the score is too thin to hold the panel together through transport, so tab routing is used instead.
Q3: How many mouse bites should a tab have?
Three or five holes at roughly 0.5mm diameter is standard, with three-hole tabs suited to smaller panels. Smaller holes leave a cleaner break edge but need more of them to carry the same load.
Q4: Which edges should the rails go on?
The two longer parallel edges of the panel, with the transport direction marked on the file. Rails on the short edges leave the long sides unsupported and expose edge components to the conveyor.
Q5: Who defines the panel outline, the fabricator or the assembler?
The array has to satisfy both, which is why it is set before files are released. WhenPCB fabrication and assembly sit with one supplier, the score depth, router path and rail dimensions are agreed against the same line rather than negotiated between two vendors.
Q6: Can depaneling cracks in ceramic capacitors be detected before shipment?
Not reliably. Optical inspection cannot see inside the ceramic body and functional tests often pass, which is why edge clearance is treated as a layout requirement rather than a final inspection screen.
Q7: Do V-score and tab routing get used on the same panel?
Yes, and on odd-shaped boards it is the normal approach. Straight separation lines run V-score while curved sections or component-dense edges run tab routing.
